1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a column redundancy fuse block.
2. Related Art
As the scaled size of semiconductor integrated circuits are reduced, the number of devices integrated in a single semiconductor chip has increased. Accordingly, the defect density of the devices also increases, thereby lowering product yield of semiconductor devices. In extreme cases, a wafer used for manufacturing the semiconductor devices must be discarded.
In order to reduce the defect density, a redundancy circuit is used to exchange defective cells with extra replacement cells. In the semiconductor devices, a redundancy circuit (or fuse circuit) can be installed corresponding to row interconnections, i.e., word lines, and column interconnections, i.e., bit lines, and may include a fuse set array for storing address information of the defective cell. The fuse set array includes a plurality of fuse sets having a plurality of fuse interconnections, wherein a program for each fuse set can be executed through a selective laser cutting (or blowing).
FIG. 1 is a plan view of a conventional semiconductor chip. In FIG. 1, a column redundancy circuit block Y-Fuse is installed in a column control block 20 to relieve the column interconnections. Here, the column control block 20 is installed between banks that are adjacent to each other in the column direction.
FIG. 2 is a block diagram of a conventional redundancy circuit unit of a semiconductor chip. In FIG. 2, the column control block 20 includes a main decoder (not shown), a predecoder 21, and a redundancy circuit unit 23.
The main decoder (not shown) is a circuit for assigning an address position, and the predecoder 21 is a circuit for generating a column selection signal by receiving a column address signal. The redundancy circuit unit 23 includes a fuse circuit unit 25 and a fuse set array 27. The fuse circuit unit 25 provides redundancy selection information to the predecoder 21 based on the fuse cutting of the fuse set array 27. Here, reference numerals 10 and 30 represent a chip and a pad area, respectively.
However, in a semiconductor device, energy (for instance, laser) is applied after a semiconductor chip has been fabricated to prevent interconnections or layers from being formed on an upper portion of a fuse set (not shown) such that the interconnections are prevented from being influenced during the fuse blowing. For this reason, data input/output interconnections are configured to detour the upper portion of the fuse set. Thus, there are limitations in the layout of the interconnections and the circuits.
In addition, although an integration density and a process technology of the semiconductor device have been improved, a pitch between fuses is not sufficiently reduced due to the laser alignment tolerance, so that the area of the fuse set array 27, i.e., an area occupied by the fuses in the semiconductor chip, may be increased. This makes it difficult to ensure the effective net die of the semiconductor chip.
In particular, the fuse circuit unit 25 and the fuse set array 27 must be aligned in a space dedicated for the redundancy circuit unit 23, so that the fuse sets constituting the fuse set array 27 must be aligned in the multi-layer structure. For this reason, the area of the column control block 20 is enlarged, so that the area of the bank cannot be increased.